Analog-to-digital conversion is a process of converting an input analog voltage (or current) into a digital format. There are many different analog-to-digital conversion architectures, such as flash, successive approximation register (SAR), pipelined, and oversampling.
Generally, oversampling has been used to implement high-resolution analog-to-digital converters (ADCs). For the conventional delta-sigma modulator or the noise-shaping SAR, the following decimation filter requires order-dependent differentiators, resulting in long latency.
On the contrary, incremental ADCs (IADCs) provide a Nyquist-like conversion with a periodic memory clearing both in the analog modulator and the digital decimator. Therefore, IADCs have drawn attention as an alternative candidate to the sigma-delta ADC for applications in sensors, wearable devices, and instrumentation for its low-latency, easy multiplexing, and simple digital filtering properties. Meanwhile, the IADC is a Nyquist-type ADC and suffers no idle tone, which allows it to become a good candidate for the high-performance audio system.
In a first-order IADC, the required number of clock cycles is 2N for an N-bit resolution. First-order structures are slow due to the required large number of clock cycles, but the first-order sample weightings are uniform, making the thermal noise reduction and the data weighting average very effective. On the other hand, a high-order structure can significantly reduce the number of clock cycles, increasing the bandwidth (BW) or reducing the op-amp power for the same BW. However, a high-order structure causes non-uniform sample weightings, reducing the effectiveness of data weighted averaging (DWA) and thermal noise suppression by oversampling.
For a second-order incremental zoom-ADC, DWA technique is utilized to diminish the impact of digital-to-analog converter (DAC) mismatch errors. The linearly decreasing weighting of the second-order structure reduces the effectiveness of the DWA technique. With an oversampling ratio (OSR) of 2 k, the achieved linearity is 6 ppm. In addition, this architecture suffers from an input-clipping problem, and it is more suitable for a dc signal. A smart dynamic element matching (DEM) algorithm from [3], determinedly selecting the capacitor elements in a Tetris' way, was proposed to compensate for the DAC element mismatch. However, the algorithm complexity increases exponentially with the order, quantizer bit, and OSR. Meanwhile, both works have a thermal noise penalty factor of 1.3. In the work by Vogelmann, et. al. [4], a dynamic integrator slicing technique was presented to reduce the first integrator's power by utilizing the input weighting function. However, there is a tradeoff between the first integrator power and the input signal power, such that the effectiveness of the integrator slicing technique depends on the weighting function. For the first order, this technique is not effective because of the originally uniform weighting, while high-order architectures inherently suffer from a thermal noise penalty (a factor of 1.8 in the third-order structure). Meanwhile, it used a single-bit quantizer to keep the linearity, because of the squarely decreasing DAC weighting. As a consequence, the loop demands power-hungry op-amps for a large output swing.
Hybrid combinations of incremental delta-sigma and Nyquist ADCs have been proposed to improve the converter efficiency. A multi-step IADC with a single op-amp [5] uses multi-slope extended counting to achieve 16-bit resolution with 320 clock cycles. With the non-amplified residue voltage being processed at the back-end stages, the limitation of the backend resolution is the comparator noise, especially at low supply. A long-conversion time is required to resolve more bits in the first stage when the overall resolution increases. In addition, the first stage employs a single-bit quantizer. Therefore, the loop needs a power-hungry op-amp. In the work from Katayama et. al. [6], a two-step scheme uses a high-resolution flash ADC and a multi-bit DAC to reduce the op-amp swing and to relax the errors in the second stage. However, the 31-level quantizer increases the areas of the flash and the DWA logic. The cyclic ADC needs an extra capacitor to store the residue voltage, which reduces the feedback factor. The two-step architecture is more sensitive to the inter-stage gain error.
In view of the deficiency of above ADCs, there is a need in the art to have a single-loop two-phase exponential incremental converter that accumulates the residue in a fast and stable approach. In particular, the incremental converter operates as a first-order IADC in the first phase to accumulate the signal linearly and suppress the thermal noise, and then the incremental ADC enables a noise coupling (NC) path to boost the signal-to-quantization-noise ratio (SQNR) exponentially in the second phase.